Free global shipping on orders over $50
TLC555IP TLC555 LinCMOS(TM) 2.1MHz 250µA Low Power Timer IC DIP-8 Package (1 Pack) - Perfect for DIY Electronics, Timing Circuits, and Industrial Control Applications
TLC555IP TLC555 LinCMOS(TM) 2.1MHz 250µA Low Power Timer IC DIP-8 Package (1 Pack) - Perfect for DIY Electronics, Timing Circuits, and Industrial Control Applications

TLC555IP TLC555 LinCMOS(TM) 2.1MHz 250µA Low Power Timer IC DIP-8 Package (1 Pack) - Perfect for DIY Electronics, Timing Circuits, and Industrial Control Applications

$5.46 $9.94 -45%

Delivery & Return:Free shipping on all orders over $50

Estimated Delivery:7-15 days international

People:19 people viewing this product right now!

Easy Returns:Enjoy hassle-free returns within 30 days!

Payment:Secure checkout

SKU:80534811

Guranteed safe checkout
amex
paypal
discover
mastercard
visa

Product Description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic, and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

Product Features

Very Low Power Consumption 1 mW Typical at VDD = 5 V

Capable of Operation in Astable Mode

CMOS Output Capable of Swinging Rail to Rail

High Output Current Capability. Sink 100 mA Typical. Source 10 mA Typical

Output Fully Compatible With CMOS, TTL, and MOS

Customer Reviews

****** - Verified Buyer

We value your privacy

We use cookies and other technologies to personalize your experience, perform marketing, and collect analytics. Learn more in our Privacy Policy.

Top